Find the effective timer clock
The timer input derives from the device clock tree. On many STM32 families, timers can receive a multiplied clock when the APB prescaler is not one. Confirm the exact rule in the clock-tree chapter for your device.
Registers are zero-based
PWM frequency = timer clock ÷ ((PSC + 1) × (ARR + 1))
With 72 MHz, PSC 71, and ARR 999, the counter runs at 1 MHz and PWM at 1 kHz. The +1 terms are the most common source of off-by-one errors.
Worked example: 1 kHz, 25% edge-aligned PWM
Scenario and inputs
Configure an STM32 timer with a 72 MHz timer input clock, PSC = 71, ARR = 999, and CCR = 250. Assume up-counting, edge-aligned operation, PWM mode 1, and active-high output polarity. The 72 MHz value is the timer input after the device clock-tree setup; it must not be assumed to equal the CPU or APB clock. This is a theoretical calculation example, not a hardware measurement.
Formula and substitution
- Counter clock = 72,000,000 Hz ÷ (71 + 1) = 1,000,000 Hz (1 MHz).
- Period counts = ARR + 1 = 999 + 1 = 1,000 counts.
- PWM frequency = 1,000,000 Hz ÷ 1,000 = 1,000 Hz (1 kHz); period = 1 ms.
- Duty cycle = CCR ÷ (ARR + 1) × 100 = 250 ÷ 1,000 × 100 = 25%.
In PWM mode 1 while counting up, the reference output is high while CNT is below CCR, so the active-high ideal is approximately 25% high time. The calculator should report 1 MHz counter clock, 1 kHz frequency, and 25% duty.
Conditions, limits, and reference
The equations assume the stated edge-aligned up-counting mode and ordinary PWM mode 1 behavior. Center-aligned or down-counting modes, repetition counters, preload/update timing, inverted polarity, dead time, and timer-specific limits can change the observed waveform or make the same formula inapplicable. STMicroelectronics RM0008 Reference Manual, section 15.3.9, describes the timer time base and PWM mode 1 edge-aligned behavior.
Duty cycle and resolution
For common edge-aligned PWM, duty cycle is CCR ÷ (ARR + 1). A larger ARR provides more compare steps and therefore finer duty resolution. Exact endpoint behavior depends on mode, polarity, preload, and update timing.
How the solver chooses
The solver searches integer PSC and ARR pairs within the selected width. It minimizes relative frequency error first and favors a larger ARR when errors are equal, preserving more duty-cycle resolution.
Verify hardware-specific behavior
Check center-aligned counting, repetition counters, complementary outputs, dead time, register width, and clock limits in the reference manual.