Find the effective timer clock
The timer input derives from the device clock tree. On many STM32 families, timers can receive a multiplied clock when the APB prescaler is not one. Confirm the exact rule in the clock-tree chapter for your device.
Registers are zero-based
PWM frequency = timer clock ÷ ((PSC + 1) × (ARR + 1))
With 72 MHz, PSC 71, and ARR 999, the counter runs at 1 MHz and PWM at 1 kHz. The +1 terms are the most common source of off-by-one errors.
Duty cycle and resolution
For common edge-aligned PWM, duty cycle is CCR ÷ (ARR + 1). A larger ARR provides more compare steps and therefore finer duty resolution. Exact endpoint behavior depends on mode, polarity, preload, and update timing.
How the solver chooses
The solver searches integer PSC and ARR pairs within the selected width. It minimizes relative frequency error first and favors a larger ARR when errors are equal, preserving more duty-cycle resolution.
Verify hardware-specific behavior
Check center-aligned counting, repetition counters, complementary outputs, dead time, register width, and clock limits in the reference manual.