STM32 Timer and PWM Calculator
Translate timer registers into frequency and duty cycle, or find a practical PSC/ARR pair for a target PWM frequency.
Calculated timer
- Counter clock
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- Timer period
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- PWM frequency
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- Duty cycle
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- Register validation
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Solver result
- PSC
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- ARR
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- Actual frequency
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- Error
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Formula and assumptions
Counter clock = timer clock ÷ (PSC + 1). PWM frequency = timer clock ÷ ((PSC + 1) × (ARR + 1)). Edge-aligned PWM duty cycle = CCR ÷ (ARR + 1) × 100%. The solver searches valid integer registers, minimizes frequency error, and breaks equal-error ties in favor of the larger ARR.
Worked example
With a 72 MHz timer clock, PSC = 71 and ARR = 999, the counter runs at 1 MHz and PWM runs at 1 kHz. CCR = 500 produces a 50% computed duty cycle.
How to use this calculator
- Enter values using the units shown beside each field.
- Choose the framing or hardware options that match your design.
- Select Calculate, then compare the result with your timing or bandwidth budget.
- Check the assumptions and your component reference manual before committing a design.
Common mistakes
- Using the APB peripheral clock when the timer receives a different effective clock.
- Forgetting the +1 applied to PSC and ARR.
- Entering a CCR value outside the useful range for the selected ARR.
- Assuming every STM32 timer has the same register width or operating mode.
Frequently asked questions
Why are PSC and ARR increased by one?
STM32 timer dividers and counters encode a zero-based value: a register value of zero represents one clock step.
Does APB prescaling affect the timer clock?
On many STM32 families, a timer clock may be multiplied when the APB prescaler is not one. Use the effective timer input clock documented for your device.
Why prefer a larger ARR?
A larger ARR provides more discrete compare values, which improves PWM duty-cycle resolution.